Tutorials

Sunday, 16 October 2016

Morning Tutorials (9:00 – 12:30)

Tutorial # 1: Fundamentals of Battery Chargers

Abstract
With the expanded use of portable, battery-operated electronic devices in every aspect of human life, there is an increased interest in the design of battery chargers integrated circuits. Since this area is not typically covered in graduate or undergraduate circuits’ curriculum, there is a serious shortage in researchers and engineers who have the necessary background to develop efficient and cost-effective solutions. This tutorial will introduce the basic operation and characteristics of various primary and secondary battery cells, such as Alkaline, NiCd, Li-Ion, and NiMH, including their charging/discharging profiles, self-discharging, internal impedance, and charging cycles. This will be followed by presenting the most common charging schemes used to charge single- and multi-cell battery stacks, including the pulse charging scheme, and the constant-current constant-voltage charging scheme. Linear and switching battery charger topologies, fuel gauging, and cell-monitoring and cell-balancing circuits will also be discussed, including examples of commercial implantations of battery charger integrated circuits.

Instructor(s): Ayman Fayed, Associate Professor, Dept. of Electrical and Computer Engineering, The Ohio State University, Columbus, OH, USA

ayman

Ayman Fayed received his Ph.D. in Electrical & Computer Engineering from The Ohio State University in 2004. From 2000 to 2009, he held several technical positions in the area of analog and mixed-signal design at Texas Instruments Inc., where he contributed to many product lines for wire-line, wireless, and multi-media devices. His work at TI included analog frontend design of high-speed wire-line transceivers, fully-integrated switching/linear regulators and battery chargers for portable media players, delta-sigma data converters for wireless standards, and on fully-integrated power management solutions for mixed-signal and RF SoCs in nanometer CMOS. Dr. Fayed joined the Dept. of Electrical & Computer Engineering at Iowa State University in 2009, where he held the Northrop Grumman Assistant Professorship. He then joined the Dept. of Electrical & Computer Engineering at The Ohio State University in 2015 as an associate professor.

He is the founder and director of the Power Management Research Lab (PMRL) and his current research interests include on-chip power grids for dynamic energy distribution in highly-integrated systems, high-frequency switching regulators with on-chip and on-package passives for SoCs, low-noise power supply modulators for RF transmitters, and energy-harvesting platforms for power-restricted & remotely-deployed systems. Dr. Fayed is a senior member of IEEE, an associate editor for IEEE TCAS-I and TCAS-II, and serves in the technical program committee of RFIC, ISCAS, and the steering committee of MWSCAS. He is the author/co-author of many publications in the field and holds 10 US patents. Dr. Fayed is a recipient of NSF CAREER Award in 2013, and the Darlington Best Transactions Paper Award from the IEEE Circuits and System Society.

Tutorial # 2: Terahertz/mm-Wave in CMOS: Design Techniques and Challenges

Abstract:
There are revolutionary achievements in silicon-based Terahertz and millimeter-wave Integrated Circuits in past few years, especially with the advancement of CMOS technology.

However, innovative design and lack of various circuit techniques still remain unknown in millimeter and sub mm-wave regimes. This tutorial presents a comprehensive studies on recent advancement on silicon-based terahertz and mm-wave integrated circuits design techniques and challenges. Active and passive components which are the atoms of high frequency circuits are revisited with high frequency design perspective. 3D EM simulators like HFSS are inseparable part of high frequency circuit design. Therefore, utilizing these tools for accurate modeling of circuit components are briefly brushed in this tutorial.

Afterward, recent terahertz and mm-wave amplifiers and transceivers are presented in details.

Instructor(s): Shahab Ardalan, Assistance Professor, Dept. of Electrical Engineering, San Jose State University, San Jose, CA, USA.

shahabShahab Ardalan (M’02–SM’10) received the B.Sc. in electrical engineering from Amirkabir University of Technology, Iran, in 1999, and the Ph.D. degree at the University of Waterloo, Waterloo, ON, Canada, in 2007. He joined the Analog Mixed Signal Research and Development Group in Gennum Corporation in 2007, where he continued his research activities on low-power, low-voltage circuits for high speed data and video broadcasting. In 2010, he joined San Jose State University, San Jose, CA, USA, as an assistant professor and director of Center for Analog and Mixed Signal where he is teaching and conducting research on topics of analog and mixed signal integrated circuits and integrated circuit security.

His research has led to several publications and patents. Dr. Ardalan is the recipient of the best paper award of ICUE’04, the CMC Industrial Award from strategic Microelectronic Council of ITAC in 2005 and the honorable mention award for communication technology changing the world in 2014 from IEEE Communications Society. He held a postgraduate scholarship from National Science and Engineering Research Council of Canada (NSERC) from 2004 to 2007, and a NSERC Post-Doctoral Fellowship award in 2010. He has been member of technical and organizing committee for number IEEE conferences and IEEE Canada Central Area Chair 2010 to 2011, member of IEEE Canada board of executive from 2004 till 2011.

Tutorial # 3 Hardware-based Security Solutions for the Internet of Things using Physical Unclonable Functions

Abstract
The Internet of Things (IoT) concept consists of numerous resource-constrained devices such as sensors, nodes and actuators that are connected together and with the Internet. By 2020 it is anticipated that the IoT paradigm will encompass approximately 20 billion connected devices. The interconnection of such devices provides the ability to collect huge amounts of data which are then processed and analyzed for further useful actions. A significant portion of the transacted data between IoT devices is private information which must, in no way, be eavesdropped or tampered with. Security in IoT devices is therefore of paramount importance for the further development of this paradigm. Such devices have typically limited area and energy resources, which makes the use of classic cryptographic solutions prohibitively expensive. Physically Unclonable Functions (PUFs) are a class of novel hardware security primitives that promise a paradigm shift in many security applications; their relatively simple architectures can answer many of the security challenges of the energy- constrained IoT devices.

In this tutorial, we discuss the design challenges of secure IoT systems and how to use hardware security to tackle those challenges, then we explain the design principles of Physically Unclonable Functions, finally we discuss the reliability and security problems of PUF devices and present a number of enhancement techniques to remedy those shortcomings. The tutorial concludes with a summary of open research questions of the design of hardware-security schemes for IoT applications.

Instructor(s): Dr Basel Halak and Professor Mark Zwolinski, Dept. of Electronics and Computer Science, Southampton University, United Kingdom.

basel

Dr Basel Halak studied with the school of Electronics and Electrical Engineering, Damascus University. He was awarded a first class honours BEng in Electronics Engineering in 2001. He then joined the MTN group, an international cellular network operator, where he worked as base station subsystems (BSS) engineer for two years. He was awarded MSc and PhD degrees in Microelectronics System Design from Newcastle University, UK in 2005 and 2009 respectively. He was then awarded a knowledge transfer fellowship to develop secure and energy efficient design for portable health care monitoring systems. In 2011, He joined the Dept. of Electronics and Computer Science at the University of Southampton, UK, where he is currently pursuing his research interests in reliable systems on a chip design technique, secure logic design, and VLSI circuits for communications. He has published a monograph and numerous IEEE papers in these areas. Dr Basel Halak is a fellow of the Higher Education Academy (HEA), and serves in the technical program committee of ICCCA, ICCCS and EWME, he is also a member of hardware security working group of the World Wide Web Consortium (W3C).

Mark

Professor Mark Zwolinski received the B.Sc. degree in electronic engineering and the Ph.D. degree in electronics from University of Southampton, Southampton, U.K., in 1982 and 1986, respectively. He is currently a Professor in the Dept .of Electronics and Computer Science, University of Southampton. He has authored two textbooks and has co-authored a third. He has written over 190 papers in the areas of EDA and test. His current research interests include high-level synthesis, fault tolerance, and behavioural modelling and simulation. Prof. Zwolinski is also a Fellow of IET and BCS and Senior Member of IEEE and ACM.

 

Tutorial # 4: Charge-Steering: A New Low-Power Design Methodology

Abstract
Recently, charge-steering circuits emerged as a possible solution to reduce the power consumption of circuits while not sacrificing their frequency of operation. As a result, charge-steering circuits quickly became favorable substitutes for their current-steering counterparts in high-speed low-power applications. This tutorial will start by explaining the theory of operation of charge-steering circuits and how they can replace their current-steering counterparts. Three major analog/mixed-signal systems are then explained with an emphasis on how they can benefit from charge steering. The first is serial-link receivers where the use of charge-steering in slicers and equalizers is emphasized. The second is analog-to-digital converters where the focus will be on the comparator design. The third is clock-and-data recovery circuits where the focus will be on the phase-interpolator design. The tutorial concludes by discussing the advantages and disadvantages of this shift towards charge-steering circuits.

Instructor(s): Sameh Ibrahim, Assistant Professor, Dept. of Electronics and Electrical Communications Engineering, Ain Shams University, Cairo, Egypt.

sameh

Sameh Ibrahim received the B.Sc. and M.Sc. degrees in electrical engineering from Ain Shams University, Cairo, Egypt, in 2001 and 2005, respectively. He received the Ph.D. degree in electrical engineering from the University of California, Los Angeles, in 2009. His Ph.D.’s thesis was entitled “High-Speed Low-Power Equalizers for High-Loss Channels”. In the summer of 2006, he joined Texas Instruments, Dallas, TX where he worked with the high-speed serial links R&D group. In the summer of 2007, he joined Mindspeed Technologies, Newport Beach, CA where he worked with the signal integrity group. From January 2010 to April 2011, he was with Marvell Semiconductor Inc., Santa Clara, CA, where he worked as a Senior Analog Design Engineer in the high-speed serial-links group. He contributed to the design of many high-speed multi-standard serial-link transceivers.

In May 2011, he became an Assistant Professor in the electronics and electrical communications engineering department of Ain Shams University, Cairo, Egypt. He was also appointed as the unit head of the Communication Systems Engineering program at Ain Shams credit hour engineering program from 2011 to 2015.

Dr. Ibrahim joined the Integrated Circuits Laboratory of Ain Shams University in May 2011 where he started his research group. Current research in the group includes: High-speed serial links design with emphasis on low power and high performance, Bio-medical applications, and Integrated power management systems including switching and linear regulators and energy harvesting.

Afternoon Tutorials (13:30 – 17:00)

Tutorial # 5: Design Methodology and Circuit Techniques for Any-Load Stable LDOs with Instant Load Regulation

Abstract
Application of the structural methodology to the LDO design creates a new class of circuits: any load stable, with instant transient response, large power supply rejection ratio and low noise. Presented are examples of the imbedded in SoC LDOs for the SRAM unit, (5 ns reaction time on the load steps), radio transmitter (shaping the required noise vs. frequency characteristic) and LDO for memory retention in the shutdown state (300 nA quiescent current). These LDOs can operate with or without off-chip load capacitors; they are robust to the process and temperature variations and portable to any CMOS process. The circuit techniques demonstrated during this course is proven in design of industrial circuits including LDO regulators. The particular topics covered in this tutorial include: LDO regulators, their parameters in steady-state and dynamic operation; line and load regulation; load step response; traditional topologies of LDO regulators; components of traditional regulators; the limitations of traditional one-loop regulators topologies. Characteristics of the proposed approach: Using specialized two and multi-loop structures, error-dependent biasing and nonlinear amplifiers. Review of compensation techniques and protection of power devices; current and temperature limits; load protection; LDO design requirements.
Four LDO design examples: a) for fast load step response, b) for low noise, c) for high PSRR, d) for nano-power quiescent current.

Instructor: Igor Filanovsky, Professor Emeritus, Dept. of Electrical and Computer Engineering, University of Alberta, Edmonton, Alberta, Canada and Vadim Ivanov, Texas Instruments, USA.

Filanovsky

Dr. I.M. Filanovsky is currently a Professor Emeritus in the Department of Electrical Engineering. University of Alberta, Edmonton, Alberta, Canada. Dr. I.M. Filanovsky is a Life Senior Member of IEEE. He has served as a Co-chair and a Technical Program Chair for the Midwest Symposium on Circuits and Systems (MWSCAS) 1990, in Calgary, and as a Session Chair for many ISCAS and MWSCAS Symposiums. He has served an Associated Editor of IEEE Transactions on Circuits and Systems, Part 1 (the terms of 2003-2005, and 2009-2011). At the present time, he is a member of IEEE Analog Technical Signal Processing Committee (Chairman 2004-2005), IEEE MWSCAS Steering Committee and is on the Editorial Board of the International Journal of Circuit Theory and Applications. Dr. I.M. Filanovsky is also the author or coauthor of about 300 publications on circuit theory, oscillations and microelectronics. He also has four patents on applied microelectronics.

Tutorial # 6: Phase-Locked Clock/Frequency Generation and Modulation

Abstract
The phase-locked loop (PLL) has been a key building block in coherent communication systems. As CMOS technology advances, the traditional PLL suffers from poor scalability, loop parameter variability, leakage current and linearity problems. Accordingly, diversified PLL architectures and circuit techniques have been proposed in consideration of performance, power and cost, thus making it more difficult for circuit designers to choose the right design solution than ever. This tutorial gives some insight into PLL basics with system perspectives tailored for circuit designers, focusing on clock/frequency generation. Also, various PLL architectures (analog/digital/hybrid) and PLL-based modulation methods (1-point/2-point/2+-point) will be discussed.

Instructor(s): Woogeun Rhee, Professor, Institute of Microelectronics, Tsinghua University, Beijing, China.

rheeWoogeun Rhee received the B.S. degree in electronics engineering from Seoul National University, Seoul, Korea, in 1991, the M.S. degree in electrical engineering from the University of California, Los Angeles, in 1993, and the Ph.D. degree in electrical and computer engineering from the University of Illinois, Urbana-Champaign, in 2001. From 1997 to 2001, he was with Conexant Systems, Newport Beach, CA, where he was a Principal Engineer and developed low-power, low-cost fractional-N synthesizers. From 2001 to 2006, he was with IBM Thomas J. Watson Research Center, Yorktown Heights, NY and worked on clocking area for high-speed I/O serial links, including low-jitter phase-locked loops, clock-and-data recovery circuits, and on-chip testability circuits. In August 2006, he joined the faculty as an Associate Professor at the Institute of Microelectronics, Tsinghua University, Beijing, China, and became a Professor in December 2011. His current research interests include short-range low-power radios for next generation wireless systems and clock/frequency generation circuits for wireline and wireless communications. He holds 22 U.S. patents.

Dr. Rhee is currently an IEEE Distinguished Lecturer of the Solid-State Circuits Society (2016-2017) and serves as an Associate Editor for IEEE JSSC. He has been an Associate Editor for IEEE TCAS-II (2008-2009) and a Guest Editor for IEEE JSSC Special Issue in November 2012 and November 2013. He has served as a member of several IEEE conferences, including ISSCC (2012-2016), CICC, and A-SSCC. He was the co-recipient of the “Silkroad Award” at the 2008 IEEE ISSCC, the “Best Student Paper Award” at the 2012 IEEE RFIT, and the “Best Paper Award” at the 2014 VLSI-DAT. He was the recipient of the “IBM Faculty Award” in 2007 and the “Advanced Employee Award” from Tsinghua University in 2012, and has been listed in “Marquis Who’s Who in the World” since 2009.

Tutorial # 7: Energy Efficiency and the Internet of Things: From Circuits to Protocols

Abstract
The Internet of Things has become the Internet of Everything and the Internet of All Things. It is predicted that by the end of 2020, the number of smart objects globally connected will reach 212 billion. Machine-to-machine (M2M) internet traffic is expected to reach up to 45% of all internet traffic. By its universal and all-inclusive nature, IoT growth over the past 5 years has been enabled by the development, design, and implementation of a heterogeneous set of data communication architectures. The objective of this tutorial is to give a comprehensive overview of the energy aspects of the internet of things at both the communication protocol level and at the circuit level. In particular, we survey the infrastructure protocols of the Internet of Things and show how energy efficiency has been the major concern driving their development and adoption. We further take a detailed look at the radio component of the IoT, which the major power consumer in the wireless sensor node. The existing wireless standards in the low GHz frequency range cannot cater to the needs of IoT Transceivers. Transceivers operating in these crowded bands need absolute frequency accuracy and external components such as crystals and/or resonators. In addition, the antenna size is too big to be integrated in a small package with the sensors. We illustrate why a paradigm shift is needed in the quest for ultra-low power transceivers with a minimalist design approach, without compromising robustness and providing a viable solution for IoT Transceivers.

Instructor(s): Ibrahim Elfadel, Professor, and Mihai Sanduleanu, Associate Professor, Masdar Institute of Science and Technology, Masdar City, Abu Dhabi, UAE.

masdarDr. Ibrahim (Abe) M. Elfadel is a Professor of Electrical Engineering and Computer Science at the Masdar Institute of Science and Technology, where he leads the Masdar Institute Center for Microsystems (iMicro). He is also the co-director of the ATIC-SRC Center of Excellence on Energy-Efficient Electronic Systems (ACE4S) and the program manager of TwinLab-MEMS, a collaborative project between the Masdar Institute and the Institute of Microelectronics in Singapore.

Between 2012 and 2015 he was the director of TwinLab-3D Stacked Chips, a Mubadala-funded, collaborative research center with the Technical University of Dresden, Germany, focused on 3D integrated circuits. From 1996 until 2010, he was a research staff member and then a senior scientist in computer-aided design (CAD) at IBM Research and the IBM Systems and Technology Group, Yorktown Heights, NY, where he was involved in the research, development, and deployment of CAD tools and methodologies for IBM’s high-end microprocessors. His current research interests include prototyping of IoT platforms; power and thermal management of multi-core processors; CAD tools and methodologies for variation-aware, low-power digital systems design; low-power, embedded digital-signal processing; modeling and integration of micro power sources, and micro-electromechanical systems.

Dr. Elfadel’s work at IBM was recognized with six Invention Achievement Awards, one Outstanding Technical Achievement Award and one Research Division Award. He was also the recipient of a Technical Leadership Award from the Association for Computing Machinery – Special Interest Group on Design Automation. Dr. Elfadel is the inventor or co-inventor of 50 issued patents, spanning the fields of integrated circuits and systems, electronic design automation, and biomedical signal processing. His published work was most recently recognized with the 2014 Donald O. Pederson Best Paper Award from the IEEE Transactions on Computer-Aided Design of Integrated Circuits. Between 2009 and 2013, Dr. Elfadel served as Associate Editor of the IEEE Transactions on Computer-Aided Design, and is currently serving as Associate Editor for the IEEE Transactions on VLSI Systems and as Associate Editor for the Microelectronics Journal (Elsevier). He obtained his PhD from MIT in 1993.

 mihaiDr. Mihai Sanduleanu is Associate Professor of Electrical Engineering and Computer Science at the Masdar Institute of Science and Technology, Abu Dhabi, UAE. He received his MSc, MEE and PhD degrees from the Technical University of Iasi, Romania, Eindhoven University of Technology, The Netherlands and University of Twente, The Netherlands in 1990, 1993 and 1999, respectively. Dr. Mihai Sanduleanu received the Philips Foundation MSc and PhD Fellowship in 1993 and 1994 respectively.

From 1999 to 2000, he was with Philips Semiconductors, Nijmegen, The Netherlands, working on fiber optic communication circuits. From 2000 to 2007 he joined Philips Research Eindhoven, The Netherlands and he was involved in Fiber Optic Interface circuits, RF IC Design, mm-Waves Transceiver design and Ultra low-power radios. While in Philips Research, Dr. Sanduleanu was Adjunct Professor in the Microelectronics group of Eindhoven University of Technology. In 2008 he had spent 6 months at Interuniversity Microelectronics Center (IMEC), Leuven, Belgium doing research on 60GHz Transceiver design and THz electronics. From 2008 to 2013, he conducted research at IBM T.J. Watson Research Center, Yorktown Heights, New York in mm-Waves transceivers for communication, imaging and RADAR, THz electronics, High-speed analog-to-digital converters for wired/wireless communication systems and Ultra low-power radios.

Dr. Sanduleanu’s area of expertise include Wireless transceiver design for RF/mm-Waves/THz communication, THz electronics, High Speed Communication Circuits for serial I/O, High speed analog-to-digital converters, Phased-Array Systems, Imaging, Fiber Optic Interface IC’s, Ultra low-power radios, Data and clock recovery and PLLs, High accuracy/low-power analog/mixed-signal circuits and systems, SoC design, On-chip sensors and actuators for autonomous transceivers (wired/wireless), High-speed digital circuits and systems, Electromagnetics and Antenna design. Dr. Sanduleanu authored/co-authored 4 books and more than 60 papers in International Conferences and Journals. He holds 51 US patents. Dr. Sanduleanu served as Associate Editor of the IEEE Transactions on Circuits and Systems between 2012 and 2013. He is currently serving as TPC Member of the 29th Conference on VLSI Design.

Tutorial # 8: Ultra-Low Power ASIC Design for Biomedical Mobile SoCs: A Digital Design Journey from Concept to a Chip

Abstract
Ultra-low power SoCs are the heart of many IoT devices in present and future products. Many emerging medical wearable devices can be realized only by mastering the design art of such SoCs. This tutorial introduces the design steps and techniques needed to design ultra-low power SoCs using digital ASIC design flow. The tutorial will introduce the steps needed to carry on ASIC design from concept to a final tape-out ready GDSII. Necessary scripts to perform simulation, Synthesis, place and route and chip finishing will be presented. The material covered will include: how to understand a chip design problem and how that affects the rest of the chip design flow; system level design and its importance for contemporary design realization; RTL development and design verification; Matlab and RTL co-simulation; synthesis, place and route, and clock-tree concepts; introduction to Design, IC, and PrimeTime Compilers; DRC & LVS challenges.

Instructor(s): Hani Saleh, Assistant Professor, Khalifa University, Abu Dhabi, UAE.

haniHani Saleh received the B.S. degree in electrical engineering from the University of Jordan, Amman, Jordan, the M.Sc. degree in electrical engineering from the University of Texas at San Antonio, San Antonio, TX, USA, and the Ph.D. degree in computer engineering from the University of Texas at Austin, Austin, TX, USA. He was with several leading semiconductor companies, including Intel, Santa Clara, CA, USA, where he was involved in ATOM mobile microprocessor design, AMD, Sunnyvale, CA, USA, where he was involved in Bobcat mobile microprocessor design, Qualcomm, San Diego, CA, USA, where he was involved in QDSP DSP core design for mobile systems-on-chip (SoCs), Synopsys, Mountain View, CA, USA, as a Key Member of the Synopsys Turnkey Design Group, where he taped out many application-specified integrated circuits (ASICs) and designed the I2C DW IP included in Synopsys DesignWare library, Fujitsu, Tokyo, Japan, where he was involved in SPARC compatible high performance microprocessor design, and Motorola Australia, Burwood East, VIC, Australia, where he was involved in M210 low power microprocessor synthesizable core design. He was a Senior Chip Designer (Technical Leader) with Apple Inc., Cupertino, CA, USA, where he was involved in the design and implementation of Apple next-generation graphics cores for its mobile products (iPad and iPhone). He has a total of 19 years of industrial experience in ASIC chip design, microprocessor design, DSP core design, graphics core design, and embedded system design. He is currently an Assistant Professor of Electronic Engineering with the Khalifa University of Science, Technology and Research, Abu Dhabi, United Arab Emirates.